As Integrated Circuits (IC) have become smaller and more complex, transistors can become more sensitive to gate delays due to perimeter variations and reduced supply voltages. The yield of low voltage digital circuits is sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Parameter deviations can be caused by statistical deviations of the doping concentration within the semiconductor device that lead to more pronounced delay variations for minimum transistor sizes. The path delay variations increase for smaller device dimensions and reduced supply voltages affecting IC performance.